1. Field of the Invention
The present disclosure relates to a thin film transistor (or “TFT”) substrate having a low resistance bus line structure and a method for manufacturing the same. Particularly, the present disclosure relates to a TFT substrate having a thick bus line buried in a substrate having a low resistance bus line structure and a method for manufacturing the same.
2. Discussion of the Related Art
Various flat panel display devices are developed to overcome many drawbacks of the cathode ray tube such as heavy weight and bulky volume. The flat panel display devices include the liquid crystal display device (or LCD), the field emission display (or FED), the plasma display panel (or PDP) and the electroluminescence device (or ED).
Flat panel display devices such as the liquid crystal display device or the organic light emitting diode display device have the substrate including a plurality of TFTs for using as the active display devices. FIG. 1 is a plane view illustrating the structure of the thin film transistor substrate used in the horizontal electric field type liquid crystal display device according to the related art. FIGS. 2A to 2E are cross-sectional views illustrating the steps of manufacturing the thin film transistor substrate of FIG. 1 by cutting along the line I-I′, according to the related art.
Referring to FIG. 1 and FIGS. 2A to 2E, the thin film transistor substrate of the LCD has a gate line GL and a data line DL crossing each other with a gate insulating layer GI therebetween on a glass substrate SUB, and a thin film transistor TFT formed at each cross section of the gate line GL and the data line DL. The crossing structure of the gate line GL and the data line DL defines a pixel area. Further included are a pixel electrode PXL and a common electrode COM for forming a horizontal electric field therebetween in the pixel area, and a common line CL connected to the common electrode COM on the substrate SUB. The gate line GL supplies the gate signal to the gate electrode G of the thin film transistor TFT. The data line DL supplies the pixel signal to the pixel electrode PXL via the drain electrode D of the thin film transistor TFT. The common line CL is formed in parallel with the gate line GL between the pixel areas and supplies a reference voltage for driving the liquid crystal to the common electrode COM.
Responding to the gate signal supplied to the gate line GL, the thin film transistor TFT can charge the pixel signal from the data line DL to pixel electrode PXL, and maintain the pixel signal on the pixel electrode PXL. The pixel electrode PXL is formed within the pixel area by being connected to the drain electrode D of the thin film transistor TFT. The common electrode COM is also formed within the pixel area by being connected to the common line CL. Particularly, the pixel electrode PXL and the common electrode COM are disposed parallel to each other in the pixel area. For example, the common electrode COM has a plurality of vertical segments which are separatedly disposed a predetermined distance from each other. The pixel electrode PXL has a plurality of vertical segments in which each segment is disposed between the segments of the common electrode COM.
At one end portion of each gate line GL and each data line DL, a gate pad GP and a data pad DP are formed, respectively. The gate pad GP and the data pad DP are connected to a gate pad terminal GPT and a data pad terminal DPT through a gate pad contact hole GPH and a data pad contact hole DPH, respectively.
Referring to FIGS. 2A to 2E again, the method for manufacturing the thin film transistor substrate according to the related art will be explained, hereinafter.
A gate metal is deposited on a substrate SUB. The gate elements are formed by patterning the gate metal using the first mask process. As shown in FIG. 2A, the gate elements include a plurality of gate lines GL extending in a horizontal direction, the gate electrode G branching from the gate line GL, and a gate pad GP formed at one end of the gate line GL. As the thin film transistor substrate is for the horizontal electric field type, the common line CL disposed in parallel to the gate line GL is further included.
A gate insulating layer GI such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the whole surface of the substrate SUB having the gate elements. After that, a semiconductor material such as amorphous silicon and an impurity dopped semiconductor material such as n+ dopped silicon are sequentially deposited thereon. By patterning the impurity dopped semiconductor material and the semiconductor material using the second mask process, a semiconductor channel layer A and an ohmic layer n are formed, as shown in FIG. 2B. The semiconductor channel layer A and the ohmic layer n overlap with the gate electrode G having the gate insulating layer GI therebetween.
A source-drain metal is deposited on the substrate SUB having the semiconductor channel layer A and the ohmic layer n. By patterning the source-drain metal using the third mask process, the source-drain elements are formed. As shown in FIG. 2C, the source-drain elements include the data line DL extending in vertical direction to cross with the gate line GL, a data pad DP formed at one end of the data line DL, the source electrode S branching from the data line DL and overlapping with one side of the gate electrode G, and the drain electrode D facing with the source electrode S and overlapping with the other side of the gae electrode G. Particularly, the source electrode S contacts one portion of the ohmic layer n to overlap with one side of the semiconductor channel layer A and the gate electrode G. The drain electrode D contacts anther portion of the ohmic layer n to overlap with the other side of the semiconductor channel layer A and the gate electrode G. Further etching the ohmic layer n using the source-drain elements as a mask, the portions of the ohmic layer n exposed between the source electrode S and the drain electrode D are removed so that the semiconductor channel layer A is exposed between the source electrode S and the drain electrode D. Consequently, the thin film transistor TFT including the source electrode S, the drain electrode D, the semiconductor channel layer A, and the gate electrode G is completed.
On the whole surface of the substrate SUB having the source-drain elements, a passivation layer PAS is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). As shown in FIG. 2D, by patterning the passivation layer PAS using a fourth mask process, a data pad contact hole DPH exposing some portions of the data pad DP and the drain contact hole DH exposing some portions of the drain electrode D are formed. At the same time, by patterning the passivation layer PAS and the gate insulating layer GI, a gate pad contact hole GPH exposing some portions of the gate pad GP and a common contact hole CH exposing some portions of the common line CL are formed.
A transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) is deposited on the passivation layer PAS having the contact holes GPH, DH, DPH and CH. By patterning the transparent conductive material using a fifth mask process, the pixel electrode PXL, the common electrode COM, the gate pad terminal GPT and the data pad terminal DPT are formed, as shown in FIG. 2D. The pixel electrode PXL contacts the drain electrode D through the drain contact hole DH, and has a plurality of segments disposed in parallel within the pixel area. The common electrode COM contacts the common line CL through the common contact hole CH, and has a plurality of segments disposed in parallel within the pixel area. The pixel electrode PXL and the common electrode COM are disposed parallel to each other with a predetermined distance therebetween. The gate pad terminal GPT contacts the gate pad GP through the gate pad contact hole GPH, and the data pad terminal DPT contacts the data pad DP through the data pad contact hole DPH.
The LCD according to the related art explained above has a problem regarding a large display area. Typically, as the area of the thin film transistor substrate increases, the gate line and the data line become longer. As the bus lines become longer, even though the resistivity of the bus line material is not changed because it is the property of the material, the resistance of the bus line becomes larger. The resistance of the bus line is defined by the following Equation 1.
                    R        =                  ρ          ⁢                      L            S                                              [                  Equation          ⁢                                          ⁢          1.                ]            
Here, R is the resistance of the bus line, ρ is the resistivity of the bus line material, L is the length of the bus line, and S is the cross-sectional area of the bus line.
That is, as the thin film transistor substrate becomes larger, the length L will be longer so that the resistance is higher. As the resistance is becomes higher, the signal passing through the bus line can be delayed. As a result, the display device has video quality problems. To solve these problems, the resistance of the bus line should be kept at a minimum. To keep the resistance of the bus line at a minimum, the cross-sectional may be increased, or the bus line material can be selected as having a lower resistivity. To select a material having a lower resistivity is very difficult because the material is limited. Furthermore, it is even possible that when the bus line becomes longer, the resistance will increase. Therefore, the best solution to minimize the resistance of the bus line is to enlarge the cross-sectional area of the bus line.
There may be two methods to increase the cross-sectional area of the bus line; one is to increase the width of the bus line, the other is to increase the thickness of the bus line. For one example, by enlarging the width of the gate bus line and/or data bus line, it is possible to prevent the resistance of the bus line from increasing. However, as the width of the bus lines defining the boundaries of the pixel area is increased, the effective pixel area should be reduced. In that case, the aperture ratio of the display area is also reduced and that causes poor display quality. For another example, by enlarging the thickness of the bus lines, the etching tact time should be longer when forming the bus lines and the space between the bus lines should be increased. This can cause the problem of a lowered aperture ratio. Furthermore, in increasing the thickness of the bus line, the step difference between the bus line and other layer can be enlarged. This causes the defects in the rubbing process of the alignment layer.
Consequently, in the thin film transistor substrate for the large diagonal area flat panel display device, the bus line structure ensuring low resistance of the bus line is an important requirement.